A High Performance Memory Allocator For Computer Systems

1366 words - 5 pages

In today’s CMOS VLSI technology makes it possible to combine a very powerful processor onto a single chip. NUMA (Non uniform Memory Access time) multiprocessor designs were of increasing importance as they were involved in supporting shared memory on a huge scale. For such systems, the placement and movement of code as well as data are crucial to performance. This needs to deal with data placement problems and this has been called the “NUMA Problem.” Presenting the programmer with an explicit NUMA memory model resulted in a significant kind of extra programming burden. The alternative is for the operating system (OS) to manage placement through the policies and mechanisms of the virtual memory subsystem. In such a system, the task of the OS-level memory management software is to determine and find out when to reference memory remotely, and when to move or copy a page to a frame in the local memory of the processor.

In 1993, system reliability analysis became important as well as complex. Although component-level analysis was well understood, system level models were difficult to develop. The behavior of the system under real workloads was extremely difficult to predict and model. However, it is not easy to predict the impact of a memory-component failure on the computer system. This depends on behavioral aspects such as the contents of the memory, the usage of the memory, and the operating system recovery techniques.The memory-access behavior of programs to determine the likelihood of an error causing a failure was studied [1]. It was found that the access behavior could account for an important number of unobserved faults. It suggested that traditional memory-reliability analysis can be fairly pessimistic in regard to field experience.

In 1995, scientists worked upon microarchitecture of HAL’s memory management unit [2].The HAL MMU is responsible for the functions such as address space translations and hardware handling,protection violation checking, data movement controls and bus interfaces among,exception handling memory coherency among caches and memories,diagnostic and the functions for caches and memories.

In recent research in high-speed network interfaces for commodity networks, has focused on removing the operating system from the critical path for sending and receiving messages. An effective solution is to provide user-level messaging so user applications can directly access the hardware of the network while keeping the remaining protected from one another. This allows messages to be sent from and received into user space without kernel intervention. Implementation difficulties arise in the mapping between the virtual addresses of message buffers specified by applications and the physical addresses required for actual transmission and reception. The network interface must be able to translate the virtual buffer addresses to physical addresses, and the translations must be coordinated with the operating system’s virtual...

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