A Novel Path Selection Method For Small Delay Defects Test

746 words - 3 pages

Aggressive technology scaling has resulted in increasing process variations and statistical diversity in manufacturing. Process variations result in varying in path lengths, and thus a possibly different set of critical paths for different process corners, necessitating consideration of process variation in delay test methods. Also, process variation adds some of near-critical paths to the critical/longest paths set [4]. Therefore, to maintain the reliability of circuits, testing methodologies need to be improved.
As technologies scales down process variation effect become more significant. Process variation causes circuit performance deviate from its initial design expectation. Therefore, it may lead to reducing the timing margins and hence, increasing the timing violation probability. As the result by shrinking the size of the transistors the importance of delay test has become more and more [10]. Process variation is a combination of systematic effects and random effects (e.g. the number of dopant atoms implanted in a transistor) which cause variation in frequency [9]. It should be noted that the random type variations especially RDF (Random Dopant Fluctuation) are dominant [14].
In order to deal with timing defects, two fault models had been used, path delay fault and transition delay fault. Small delay defects (SDD) are one type of delay defects which is affected by variations like process variation, cross-talk and power supply noise effects. SDDs introduce a small amount of extra delay to design [10] in new technology scales. The delay introduced by SDD is small, but the overall impact can effect on the performance of the target circuit if the sensitized path is critical. In order to capture cumulative effect of small delay defects, path delay test should be considered instead of transition delay test which could capture large change of delay. Due to variations, the delay of each path has certain probability longer than the clock period. Under process conditions there are multiple paths which have maximum delay. Thus a small number of paths as a candidate set of all critical paths of the circuit are able to cover a large process space. Hence, path selection is an optimization problem.
Finding a proper set of paths with most coverage is the basic problem in path selection...

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