With increasing design complexity, effective and comprehensive verification of hardware and embedded systems,
especially functional verification, has become a key concern in
VLSI and hardware/software system development .
It is generally believed the majority of RTL design efforts are spent in
functional verification .
Murphy's Law states ``if anything can go wrong, it will.''
Even brilliant engineering projects can be marred by trivial mistakes.
Some well-known examples include Intel's Pentium floating-point division bug ,
Mars Climate Orbiter crash ,
and Apple's iPhone antenna problems .
The importance of verification can never be over-emphasized.
In functional verification, we try to ...view middle of the document...
For example, let us consider a simple processing unit shown in Figure .
The design takes 3 inputs: a 16-bit address, a 2-bit OpCode and a 16-bit data.
To specify functional coverage, we may want to divide the 64K addressing space
into 3 ranges of value, or bins: the LOW and HIGH bins cover the lowest and highest
256 addressing space respectively, while the MAIN bin cover the bulk of the addresses
in the middle. Similarly, we can define separate bins for each OpCode value.
Historically, most of the interesting bugs were found in corner cases.
These corner cases are typically located in cross coverage bins of multiple coverage points.
Verification engineers typically specify interesting corner cases
as cross coverage bins.
As in our example, the verification engineer may be interested in specific corner cases, such as
when address is LOW and OpCode is READ, or address is HIGH and OpCode is WRITE.
The corresponding coverage requirements written in SystemVerilog
can be found in Figure .
This phenomenon has long been utilized empirically by engineers, yet no rigorous analysis of cross coverage has been proposed.
In this paper, we focus on verification targeting a user specified set of
cross coverage bins, and quantify the probabilities of finding bugs there.
The rest of this paper is organized as follows. In Section 2,
we summarize prior work on coverage-driven constrained random verification.
In Section 3, we demonstrate the advantage of cross coverage.
In Section 4, we present our generalized cross coverage model,
and analyze the probability
of finding the bug within a given number of samplings and the expected number
of samples until bug detection based on our cross coverage model using
random, round-robin, and hybrid sampling strategies in recurring and
In Section 5, we conduct experiments using Monte Carlo simulation
which indicate our probability formulas are correct.
We conclude in Section 6.
Yuan et al. proposed the use of constraints and biasing to form
a simulation environment in functional verification.
They used Binary Decision Diagrams (BDDs)