III. ARCHITECTURE IMPLEMENTATION
Based on implementation of FMULT_ACCUM and control unit, this system was implemented in three different types. Bit serial, pipeline and single resource. This paper discusses the design and implementation of bit serial architecture. The main motive behind bit serial implementation was to reduce the area and cost at the expense of speed.
Figure 2. FMULT_ACCUM Implementation
Figure 2 shows the implementation of FMULT_ACCUM. Inputs to the FMULT block are two’s complement and floating point parallel input. Output of this block is two’s complement 1 bit serial output. A four bit Count_in signal is used as a counter which avails FMULT to repeat operations after ...view middle of the document...
This is shifted serially and the input is given to accumulator.
Table 1. Allocation of clock cycles for FMULT block
Clock Cycles 0 1 2 to 6 7 8 9 to 14 15
Operation CLR EXP
CLR MULT MULT MANT >>4 and -3 LD OUT
TC to FL LD An LD SR ADD EXP FL to TC
Since the implementation this design is in bit serial fashion, we optate the size of the accumulator to be one bit. It consists of a one bit full adder with 16 bit shift register. Figure 3 shows a simple one bit accumulator. The two mux are used to select between zero and the output of the previous stage. Initially zero is selected clearing the carry and the shift register. The result will be stored serially and will be shifted out in parallel. The outputs partial signal estimate (SEZI) and signal estimate (SEI) is the sum of first six and eight predictor outputs as shown in Equations 3 and 4. The first iteration deals with resetting the registers. Hence the output will be loaded out at seventh and ninth iteration for SEZI and SEI respectively.
SEZI = WB1+WB2+WB3+WB4+WB5+WB6 (3)
SEI = SEZI+WA1+WA2 (4)
Figure 3. Accumulator Implementation
The operation of the accumulator is as follows. In the first 16 cycles, the accumulator is reset. It takes 16 cycles because...