Low Power Noise Tolerant Latch Design

2134 words - 9 pages

In this paper an ultra low power and probabilistic based noise tolerant latch is proposed based on Markov Random Field
(MRF) theory. The absorption laws and H tree logic
combination techniques are used to reduce the circuit complexity of MRF noise tolerant latch. The cross coupled
latching mechanism is used at the output of the MRF latch inorder to preserve the noise tolerant capability of MRF latch. The proposed latch is faster than the latches presented in the literature and provides low power and high noise immunity.
Hence we can achieve good trade off in terms of performance, robustness and cost. The latches are evaluated in 180nm CMOS technology. The results obtained show that the proposed latch consumes low power and highly noise tolerant.
Finally the proposed latch is applied in transmission gate based full adder circuit. In 180nm technology the proposed adder can operate reliably with superior noise tolerance and low power compared to conventional latch based full adder
circuit.

Keywords-Markov Random Field (MRF) latch, Markovian Property, C-element, Single Event Upset (SEU), Soft error tolerant, Root Mean Square (RMS) noise voltage.

1. INTRODUCTION
CMOS technology is approaching the nano-electronics range
nowadays, but experiences some practical limits. High dynamic power dissipation and leakage current in deep submicron technologies contribute a major proportion of total power dissipation in CMOS circuits designed for portable applications. Today, there are an increasing number of portable applications requiring small-area, low-power and high-throughput circuitry .Lowering the supply voltage appears to be the most well known means to reduce power consumption. Power consumption has become one of the biggest challenges in high-performance logic circuit design. Designers are thus continuously challenged to come up with innovative ways to reduce power[4], while trying to meet all the other constraints imposed on the design. However, lowering supply voltage also increases circuit delay and degrades the drivability of cells designed with certain logic styles. The lower threshold voltage will cause a decrease in noise-tolerance. Moreover, noise does not scale down proportionally as supply voltage decreases. As the size of CMOS devices continues to scale down to the nanometer scale, signal errors caused by noise can significantly affect the circuit performance. The circuits operate at low noise margins and thus VLSI circuits are more sensitive to noise [1-3]. The MRF approach is further extended to the design of a probabilistic-based noise-tolerant sequential circuit in this paper.

2. SEQUENTIAL CIRCUITS
Sequential circuits are classified into latches and flip-flops,
where flip-flops are edge triggered sequential circuits and latches are level sensitive sequential circuits. When the noise affects the input signal, the latch will be affected during the entire transparent period...

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