Mplementation Of Fsm Mbist And Design Of Hybrid Mbist For Memory Cluster In Asynchronous So C

1220 words - 5 pages

Today’s SoC’s are memory dominant. More than 90% of physical area is dominated by memory according to the ITRS [International Technology Roadmap for Semiconductors] [3]. As memories become denser, they are more prone to defects and faults are more complex. Using external Automatic Test Equipment (ATE) will become expensive for dense memories due to pin inductance and tester pins cost [11]. Also, at-speed testing is not possible. Test time increases as the number of memories increase in a chip. An on-chip at-speed testing technique is the call of the hour. BIST is a Design for Test (DFT) technique [2] in which part of the circuit is used to test the circuit itself. MBIST is the most widely used technique for testing memories. MBIST technique integrates the functionality of automatic test equipment on the same die as embedded memories. It provides high speed testing and also testing can be done during operation and maintenance stage even outside the electrical testing environment.
There are two widely used techniques for MBIST. FSM based MBIST and microcode based MBIST. In FSM based MBIST, control signals for BIST controller operations are defined as state machines [8]. It is hardwired. Microcode based MBIST has a Programmable Memory BIST (P-MBIST) controller. It has flexibility of programming new test algorithms into the controller as and when needed, but suffers from area overhead [8].
The paper is organised as follows. Section II describes FSM based MBIST and introduces a hybrid MBIST scheme called FSM-based Programmable MBIST. Section III describes various MBIST algorithms. Section IV describes Design Under Test (DUT) for hybrid MBIST and the proposed MBIST Controller.FSM based BIST has a number of states. This technique uses 1 test algorithm for test operation. In the proposed paper, MARCH C- algorithm is used. This algorithm is chosen because it is simple and yet can detect many faults like stuck-at faults, address decoder faults, transition faults and some coupling faults [9].Figure 1 Shows block diagram for FSM based MBIST Architecture. In the block diagram Start, rst, Clk, Sys_datain, Sys_addr are input signals, ramout and fail are the output signals. The blocks in Figure 1 are Address generator, Single -port Memory, Comparator and Multiplexers. The Address generator is a counter which generates address for the memory to be tested. It can count up or down to provide address in ascending or descending order. Comparator compares the datain and ramout, if they are not equal fail signal is raised, else, pass signal is raised. The multiplexer chooses between normal mode and test mode. When start=1, test mode is selected. Figure 2 shows the State Diagram for implemented FSM MBIST. The faults covered by this architecture are Address Decoder Faults, Transition Faults and Stuck-at Faults [2] The FSM MBIST has low area and good fault coverage. The percentage of fault coverage depends on the MARCH algorithm used. But since FSM MBIST is hard-wired,...

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